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FUNCTIONAL DESCRIPTIONS
INTRODUCTION
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
The 33927 provides an interface between an MCU and the
large FETs used to drive three-phase loads. A typical load
FET may have an on-resistance of 4.0m ? or less and could
require a gate charge of over 400 nC to fully turn on. The IC
can operate in automotive 12V to 42V environments.
Because there are so many methods of controlling three-
phase systems, the IC enforces few constraints on driving the
FETs. It does provide deadtime (cross-over) blanking and
logic, both of which can be overridden, ensuring both FETs in
a phase are not simultaneously enabled.
A SPI port is used to configure the IC modes.
FUNCTIONAL PIN DESCRIPTION
PHASE A (PHASEA)
This pin is the totem pole output of the Phase A
comparator. This output is low when the voltage on Phase A
high-side source (source of the High-Side load FET) is less
than 50 percent of VBAT.
POWER GROUND (PGND)
This pin is power ground for the charge pump. It should be
connected to VSS, however routing to a single point ground
on the PCB may help to isolate charge pump noise.
NOTE: This is NOT the same as the Phase Grounds for
each of the Phases.
ENABLE 1 AND ENABLE 2 (EN1, EN2)
Both of these logic signal inputs must be high to enable
any gate drive output. When either or both are low, the
internal logic (SPI port, etc.) still functions normally, but all
gate drives are forced off (external power FET gates pulled
low). The signal is asynchronous.
When EN1 and EN2 return high to enable the outputs,
each LS driver must be pulsed on before the corresponding
HS driver can be commanded on. This ensures that the
bootstrap capacitors are charged.
RESET (RST)
When the reset pin is low the integrated circuit (IC) is in a
low power state. In this mode all outputs are disabled, internal
bias circuits are turned off, and a small pull down current is
applied to the output gate drives. The internal logic will be
reset within 77ns of RESET going low. When RST is low, the
IC will consume minimal current.
This input should not be driven above the VDD voltage.
CHARGE PUMP OUT (PUMP)
This pin is the switching node of the charge pump circuit.
The output of the internal charge pump support circuit. When
the charge pump is used, it is connected to the external
pumping capacitor. This pin may be left floating if the charge
pump is not required.
CHARGE PUMP INPUT (VPUMP)
This pin is the input supply for the charge pump circuit.
When the charge pump is required, this pin should be
connected to a polarity protected supply. Typical applications
would connect it to VBAT. This input should never be
connected to a supply greater than 40V.
If the charge pump is not required this pin may be left
floating.
VBAT INPUT (VBAT)
This pin should be connected to the system battery
voltage. It is used to provide power to the internal steady
state trickle charge pump and to energize the hold-off circuit.
It is also the reference bias for the Phase Comparators and
Desaturation Comparator.
PHASE B (PHASEB)
This pin is the totem pole output of the Phase B
comparator. This output is low when the voltage on Phase B
high-side source (source of the High-Side load FET) is less
than 50 percent of VBAT.
PHASE C (PHASEC)
This pin is the totem pole output of the Phase C
comparator. This output is low when the voltage on Phase C
high-side source (source of the High-Side load FET) is less
than 50 percent of VBAT.
PHASE A HIGH-SIDE INPUT (PA_HS)
This input logic signal pin enables the High-Side Driver for
Phase A. The signal is active low, and is pulled up by an
internal current source.
PHASE A LOW-SIDE INPUT (PA_LS)
This input logic signal pin enables the Low-Side Driver for
Phase A. The signal is active high, and is pulled down by an
internal current sink.
VDD VOLTAGE REGULATOR (VDD)
This pin is an internally generated 5V supply. The internal
regulator provides continuous power to the IC and is a supply
33927
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
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